With respect to the CPU of the personal computer, 60% out of all cycles are read cycles. It means that the length of the read cycle is a dominant factor for the performance of the system (especially for the speed performance). The major reason influencing the length of the read cycle is the read cycle of the DRAM (Dynamic Random Access Memory).
For understanding the internal signals inside a microprocessor system, some related issues are briefly described here.
1. L2 Cacheable Cycle
It means that a cycle having a corresponding address inside the L2 Cache (which is a kind of SRAM). During this cycle, the data can be directly read from and written into the L2 Cache instead of the DRAM.
2. Cache HIT/MISS (K HIT/MISS)
Judge whether an address corresponding to a cycle is related to the L2 Cache. If the answer is yes, it is called "Cache HIT"; and if the answer is no, it is called "Cache MISS".
3. ONBDM
Judge whether an address corresponding to a cycle is related to the DRAM. If the answer is yes, the signal ONBDM equals 1. And the cycle will be stopped by a memory controller and a DRAM cycle will be initiated. If the signal ONBDM equals 0, other devices (such as PCI Bus or ISA bus) are responsible for this cycle.
4. Page Hit
This signal means that two neighboring sets of data addresses are inside a same page of the DRAM.
5. Page Miss
This signal means that two neighboring sets of data addresses are not inside a same page of the DRAM.
6. ADS#
This is a control signal from the CPU. This signal represents that the CPU starts a work cycle.
7. Burst Ready
It is a control signal from a chip controller. This signal informs the CPU that the system has completed the present work cycle.
8. Lead Off Time
This means the time interval between the CPU outputting an ADS# and the CPU receiving the first set of data corresponding to this ADS# (that is, Burst Ready is received).
9. RAS# (Row Address Strobe)
This is a control signal related to the DRAMs and an active low signal. That is, when RAS# changes from 1 to 0, according to an address from the Memory Address Bus (MA), the DRAM will read the data from the location corresponding to said address.
10. CAS# (Column Address Strobe)
This is a control signal related to the DRAMs and an active low signal. That is, when CAS# changes from 1 to 0, according to an address from the Memory Address Bus (MA), the DRAM will read the data from the location corresponding to said address.
11. Tag RAM
The Tag RAM is an independent SRAM. The Tag RAM includes the addresses corresponding to all data stored in L2 Cache.
12. EDO/Fast Page Mode DRAMs
The EDO Mode DRAM and the Fast Page Mode DRAM are two different DRAMs. Although the control signals of these two DRAMs are the same, the EDO Mode DRAM is more progressive and needs more advanced technology. In addition, for achieving the same data access, the EDO Mode DRAM requires less time. When the DRAM control signals (for example, CAS#) changes from 0 to 1, the data from the EDO Mode DRAM will still stay in the Memory Bus; whereas, for the same situation, the data from the Fast Page Mode DRAM will disappear when the control signals disappear.
Generally speaking, after the internal control signals of the microprocessor system are decided, the DRAM controller of the microprocessor system starts to work. These control signals comprise the comparison results of some signals. For example, the addresses of the present cycle are compared to identify whether the cycle is L2 Cacheable Cycle (i.e., for KHIT, to identify whether the cycle is related to the SRAM) or whether ONBDM equals 1 (that is, identify whether the cycle is related to DRAM). To identify whether the cycle is Page Hit (where two neighboring sets of data are inside a same page of the DRAM) or Page Miss (where two neighboring sets of data are not inside a same page of the DRAM) is also executed. In addition, the time when the DRAM receives the control signals and the time when the data in the DRAM are read are also to be determined (it is to be noticed that by determining CAS#/RAS#, the memory address can also be determined, and whether CAS#/RAS# is determined depends on Page Hit/Page Miss). Therefore, only after all control signals are stable, the microprocessor will drive the DRAMs. Otherwise, the microprocessor will read the wrong data from the wrong DRAM locations.
With respect to the related technology, the Lead Off time of the DRAM is limited to the applied circuit elements. For example, a 15 ns SRAM is used as the address-storing Tag RAM to serve as a synchronous L2 Cache. Till the second time interval, the correct address can be obtained by the Tag RAM (where the first time interval is for initialing ADS#). After some buffers, combination circuits, delay consideration, and element preset time consideration are incorporated, CAS#/RAS# can be determined in the third time interval. When the EDO/Fast Page Mode DRAMs are used for the memory elements, the total data-reading cycle will be up to 6 time intervals. Even when the faster memory elements are used, concerning the data-reading cycle, only one time interval is reduced.
From the above it is seen that a method for effectively shortening the data-reading cycle in a data reading and writing system is often desired.